The present invention relates to an analog-to-digital converter, and more specifically to a xcex94xcexa3 A/D converter constituted of a combination of an oversampling and a noise shaping.
An oversampling A/D converter not only can minimize a quantization noise in a signal band but also can realize a highly precise conversion by making a sampling frequency greatly higher than a Nyquist frequency which is a double of signal band frequency. Namely, a ratio of a signal power to a noise power (called a xe2x80x9cSN ratioxe2x80x9d hereinafter) is increased. The reason for this is as follows:
The quantization noise generated in a quantizer for converting an analog signal into a digital signal, is a white noise which generates irregularly and distributes over the whole of a frequency region. Assuming that the sampling frequency of the oversampling A/D converter is fs, the noise power distributes from DC to fs/2. If the sampling frequency is remarkably larger than the signal band, the noise power in the signal band correspondingly becomes small. The noise power distributing out of the signal band can be removed by a decimation filter which is located at a later stage in an ordinary practice.
Therefore, the larger the ratio of the sampling frequency fs to the Nyquist frequency fn (called an xe2x80x9coversampling ratioxe2x80x9d hereinafter) is, the SN ratio becomes larger.
A xcex94xcexa3 A/D converter, which is one kind of the oversampling A/D converter, is a technology having a frequency characteristics of a high pass filter for a noise power distributed from DC to fs/2, so as to further decrease the noise power in a low frequency region. Accordingly, the noise power in the signal band is further reduced. In general, a technology of expelling the noise power in the signal band to the outside of the signal band is known as a noise shaping.
FIG. 10 illustrates a basic structure of a conventional xcex94xcexa3 A/D converter. This comprises an analog adder 1 for obtaining a difference between an analog input signal X(z) and an output of a one-bit D/A converter provided in a feedback part, an analog integrator 2 for integrating an output of the analog adder 1, an one-bit quantizer 3 for converting an output of the analog integrator 2 into a digital value, a delay 8 for holding an output of the one-bit quantizer 3 until a next sampling time, and the one-bit D/A converter 6 for converting a one-bit data of the delay 8 into an binary analog signal. A digital output of the one-bit quantizer 3 constitutes an output Y(z) of this xcex94xcexa3 A/D converter. Incidentally, the analog integrator 2 has a characteristics of a low pass filter for allowing to only a low frequency component to pass and for cutting off a high frequency component. Seeking a transfer function of this structure, it becomes the following expression (1):
Y(z)=X(z)+(1xe2x88x92zxe2x88x921)Q(Z)xe2x80x83xe2x80x83(1)
In this case, since only one analog integrator is provided in a closed loop, the shaping noise of a first-order can be realized. For example, in a xcex94xcexa3 A/D converter having two analog integrators in a closed loop, the noise shaping of a second-order is realized, thereby to increase a noise suppression in the signal band.
In a Nyquist sampling A/D converter performing a sampling at a Nyquist frequency, the precision of conversion is determined by precision in the circuit in a voltage axis. In the oversampling xcex94xcexa3 A/D converter, however, it is possible to increase the SN ratio by increasing the oversampling ratio or increasing the order of the noise shaping. In other words, since the oversampling xcex94xcexa3 A/D converter is a technology for increasing the precision of conversion in a time axis, the precision in the circuit in a voltage axis can be relaxed. Therefore, the precision of conversion is bounded by 12 bits in the Nyquist sampling A/D converter, but the oversampling xcex94xcexa3 A/D converter can obtain a further high precision of conversion. For example, in an audio band having a signal band of about 20 kHz, if the oversampling ratio is 64 times with the noise shaping of a third-order, the sampling frequency becomes about 2.5 MHz. In this case, the precision of conversion of 16 bits can be sufficiently realized.
However, considering to what degree a convertible signal band can be enlarged while the precision of conversion, a several 100 kHz is an upper limit. For example, if it is attempted to obtain the precision of conversion compatible to the above example in the signal band of 1 MHz, the sampling frequency becomes 128 MHz with the noise shaping of the third-order. In this case, an unity gain frequency of an operational amplifier used in the integrator is required to be on the order of 500 MHz. However, it is very difficult to design such an operational amplifier, and although it possible, a consumed electric power remarkably increases. If the order of the noise shaping is increased to a fourth-order or A fifth order, the oversampling ratio can be lowered. However, if the order of the noise shaping exceeds the third-order, the closed loop becomes unstable.
In order to realize a stable structure, it is necessary to give an attenuation coefficient (0 less than ai less than 1) to the integrator, so that an output amplitude of the integrator never becomes large. For example, FIG. 11 illustrate a basic structure of a stability-considered xcex94xcexa3 A/D converter realizing the noise shaping of the third-order. Three analog integrators are provided, and an analog multiplier 9a, 9b and 9c is located behind each analog integrator. The transfer function is expressed by the following expression (2):
Y(z)={a1a2a3X(z)+(1xe2x88x92zxe2x88x921)Q(z)}/f(z)xe2x80x83xe2x80x83(2)
where
f(z)=1+(a1a2a3+a2a3+a3xe2x88x923)zxe2x88x921+(3xe2x88x92a2a3+2a3) zxe2x88x922+(a3xe2x88x921) zxe2x88x923
Namely, the signal component is attenuated by the product xe2x80x9ca1a2a3xe2x80x9d of attenuation coefficients of the respective integrators. Therefore, even if the order is increased, it is not possible to estimate an increase of the SN ratio as expected.
Now, a multi-bit xcex94xcexa3 A/D converter is known, which comprises, as shown in FIG. 12, an n-bit quantizer 4 for converting an analog signal into a digital signal of a multi value, and an n-bit D/A converter 7 for converting the multi-bit digital signal of the multi value into an analog signal of a multi value, in place of the one-bit quantizer 3 and the one-bit D/A converter 6. In this A/D converter, by increasing the resolution of the quantizer, the quantization noise Qxe2x80x2(z) becomes small and the noise power distributed over the whole frequency region is decreased. In general, by increasing the resolution of the n-bit quantizer 4 by each one bit, the SN ratio is elevated by each 6 dB. However, the n-bit D/A converter 7 has a non-linear error E(z). The transfer function of the multi-bit xcex94xcexa3 A/D converter shown in FIG. 12 becomes as the following equation (3):
xe2x80x83Y(z)=X(z)+E(z)+(1xe2x88x92zxe2x88x921)Qxe2x80x2(z)xe2x80x83xe2x80x83(3)
The non-linear error E(z) of the n-bit D/A converter 7 is added to the analog signal X(z) with no modification, and the noise shaping is not made. Namely, the SN ratio is remarkably deteriorated by this non-linearity. Therefore, the n-bit D/A converter 7 is required to have the precision comparable to the precision of conversion in the A/D converter. However, it is very difficult to realize the n-bit D/A converter 7 mentioned above, and the circuit scale greatly becomes large. For example, in the case that the n-bit D/A converter 7 is realized in an integrated circuit, many capacitors are required. If a 16-bit D/A converter is constituted using 216 unitary capacitors of 5 xcexcm square, a size variation to be controlled in a fabricating process is 4.9 nm, which is a value difficult to realize. In addition, even if such very small capacitors are used, the total area of the capacitors occupies a large area of 1.3 mm square.
One technology for overcoming this problem is disclosed in xe2x80x9cAn improved xcex94xcexa3 modulator architecturexe2x80x9d, 1990, IEEE, ISCAS, pp372-375, and in U.S. Pat. No. 4,987,416. FIG. 13 illustrates a one-order basic structure of this technology. An analog adder I subtracts from an analog signal X(z) a feedback signal outputted from a one-bit D/A converter 6. An output of the analog adder 1 is supplied to an analog integrator 2, and an output of the analog integrator 2 is digitized by an n-bit quantizer 4. Here, a quantization noise Qa(z) is mixed into. From an n-bit output of the n-bit quantizer 4, only the most significant bit is extracted by a most significant bit extractor 5. Here, a digital quantization noise Qd(z) is mixed into. This most significant bit is held by a delay 8a until a next sampling time, and then, is supplied to a one-bit D/A converter 8a for converting the received signal into a binary analog value. Qd(z) mixed into by the most significant bit extractor 5 is held by a delay 8b until the next sampling time, and is added to the output of the n-bit quantizer 4 at the next sampling time by a digital adder 10. An output of the digital adder 10 constitutes an output Y(z) of this A/D converter. Here, assuming that the output of the n-bit quantizer 4 is Yxe2x80x2(z), the transfer function of Yxe2x80x2(z) becomes as the following expression (4):
Yxe2x80x2(z)=X(z)+(1xe2x88x92zxe2x88x921)Qa(z)xe2x88x92zxe2x88x921Qd(z)xe2x80x83xe2x80x83(4)
Accordingly, the transfer function of the output Y(z) of this A/D converter becomes as the following expression (5):
Y(z)=X(z)+(1xe2x88x92zxe2x88x921)Qa(z)xe2x80x83xe2x80x83(5)
Namely, Qd(z), which is far larger than Qa(z), is removed. In this method, since only the most significant bit is fed back, it is possible to use the one-bit D/A converter 6. Since the one-bit D/A converter 6 outputs a binary analog value, the non-linear error E(z) is not essentially mixed into. The expression (5) becomes equal to the transfer function of the expression (3) when E(z)=0, so that the SN ratio comparable to that in the prior art multi-bit xcex94xcexa3 A/D converter can be expected.
FIG. 14 illustrate a similarity of FIG. 13. The analog adder 1 subtracts from the analog signal X(z) the feedback signal outputted from the one-bit D/A converter 6. The output of the analog adder 1 is supplied to the analog integrator 2, and the output of the analog integrator 2 is digitized by the n-bit quantizer 4. Here, the quantization noise Qa(z) is mixed into. From the n-bit output of the n-bit quantizer 4, only the most significant bit is extracted by the most significant bit extractor 5. Here, the digital quantization noise Qd(z) is mixed into. This most significant bit is held by the delay 8a until a next sampling time, and then, is supplied to the one-bit D/A converter 8a for converting the received signal into a binary analog value. Qd(z) mixed into by the most significant bit extractor 5 is supplied to a differentiator 12 which outputs a difference from Qd(z) before one sampling time. A difference between the output of the most significant bit extractor 5 and an output of the differentiator 12 is obtained by a digital adder 10. This is an output Y(z) of this A/D converter. Here, assuming that the output of the most significant bit extractor 5 is Yxe2x80x3(z), the transfer function of Yxe2x80x3(z) becomes as the following expression (6):
Yxe2x80x3(z)=X(z)+(1xe2x88x92zxe2x88x921)Qa(z)+(1xe2x88x92zxe2x88x921)Qd(z)xe2x80x83xe2x80x83(6)
Accordingly, the transfer function of the output Y(z) of this A/D converter becomes as the following expression (7):
Y(z)=X(z)+(1xe2x88x92zxe2x88x921)Qa(z)xe2x80x83xe2x80x83(7)
Namely, the expression (7) is equal to the expression (5), and it has a performance equivalent to the structure shown in FIG. 13.
Similarly, the structure of the second-order and the third-order noise shaping, as disclosed in the above referred publications, is shown in FIG. 15 and FIG. 16. Their similarity is shown in FIG. 17 and FIG. 18. The transfer function of the structure shown in FIG. 15 and FIG. 17 becomes as the following expression (8):
Y(z)=X(z)+(1xe2x88x92zxe2x88x921)2Qa(z)xe2x80x83xe2x80x83(8)
The transfer function of the structure shown in FIG. 16 and FIG. 18 becomes as the following expression (9):
Y(z)=X(z)+(1xe2x88x92zxe2x88x921)3Qa(z)xe2x80x83xe2x80x83(9)
The system disclosed in the above referred publications has the following problems. In the conventional xcex94xcexa3 A/D converter using the one-bit quantizer, the quantization is carried out by comparing the output of the integrator with one threshold level of the quantizer. Accordingly, no limit exists in the amplitude of the output of the integrator, so that even if the output of the integrator is very large, the output of the quantizer does not change. However, in the multi-bit xcex94xcexa3 A/D converter, since the quantizer supplies an output of a plurality of bits, the quantizer has a plurality of threshold levels. Accordingly, the output of the integrator must be restricted to the same extent as a full scale of the quantizer. For example, if a four-bit quantizer is used, a outputted digital data is a hexadecimal value. Therefore, the quantizer is required to have 15 threshold levels. Assuming that the full scale of the input voltage of the quantizer is xe2x88x921V to +1V, a voltage corresponding to one LSB becomes 125 mV. Accordingly, if the amplitude of the output voltage of the integrator is in the range of xe2x88x921.0625V to +1.0625V, the quantization noise uniformly distributes with the maximum value of xc2x162.5 mV. However, the amplitude of the output voltage of the integrator is out of this range, the quantization noise is locally greatly mixed in the proximity of a maximum value or a minimum value of the input voltage. As a result, the SN ratio is deteriorated.
FIG. 19 illustrates the result of a function simulation of the system disclosed in the above referred publications. This is the result of the four-bit quantization in the one-order structure shown in FIG. 13 or FIG. 14. The full scale of the input voltage of the quantizer is xe2x88x921V to +1V, but the amplitude of the output voltage of the integrator exceeds this range. Therefore, the digital output includes a distortion in portions corresponding the maximum value and the minimum value of the input voltage, with the result that the SN ratio is deteriorated. The SN ratio of 53 db is obtained, which is lower than 59 dB of the SN ratio obtained in the simulation in a multi-bit xcex94xcexa3 A/D converter of the first-order, four-bit quantization and four-bit feedback, under the same condition.
In order to avoid this problem, it is necessary either to restrict the amplitude of the analog input of the A/D converter or to add an analog multiplier to the integrator so as to attenuate the input by a gain coefficient xe2x80x9caxe2x80x9d (0 less than a less than 1), thereby to suppress the amplitude of the output of the integrator. In the former manner, even if the amplitude of the output of the integrator can be suppressed within the full scale of the quantizer, the peak SN ratio becomes low by a suppressed portion of the signal amplitude. FIG. 20 illustrates a structure having an analog multiplier in the latter manner. The transfer function in this structure becomes the following expression (10):
Y(z)={aX(z)+(1xe2x88x92zxe2x88x921)Qa(z) +(1xe2x88x92a)zxe2x88x921 (1xe2x88x92zxe2x88x921)Qd(z)}/{1+(axe2x88x921)zxe2x88x921}xe2x80x83xe2x80x83(10)
From the expression (10), the smaller the value of xe2x80x9caxe2x80x9d is, Qd(z) is leaked in. Accordingly, the SN ratio is remarkably deteriorated. FIG. 21 illustrates the result of the function simulation in the case that the coefficient of the analog multiplier 9a is xe2x80x9caxe2x80x9d=0.5 in the first-order, four-bit quantization under the same condition mentioned above. It would be seen that, the amplitude of the integrator is suppressed within the input full scale of the quantizer, so that the quantization is normally carried out, and on the other hand, Qd(z) is leaked in the digital output after the digital processing has been carried out, a high frequency noise is mixed into. The SN ratio obtained under this situation is 47.6 dB.
As mentioned above, the system disclosed in the above referred publications has the following problems: First, since the one-bit feedback is adopted, the signal of the difference from the analog signal becomes large, so that the output amplitude of the integrator becomes large. It is necessary to suppress the output amplitude of the integrator within the input full scale of the quantizer, and therefore, the analog multiplier 9a becomes necessary. The coefficient xe2x80x9caxe2x80x9d of the analog multiplier must be smaller than xe2x80x9c1xe2x80x9d. At this time, the digital quantization noise Qd(z) to be removed is leaked into. Since Qd(z) is greatly larger than the quantization noise Qa mixed into with the quantizer, the SN ratio is greatly deteriorated.
The present invention was made in consideration of the above mentioned matters. Accordingly, it is an object of the present invention to provide a new multi-bit xcex94xcexa3 A/D converter comprising a digital processing circuit capable of removing, without using an attenuation coefficient of an integrator, a digital quantization noise generated in a process in which an n-bit quantizer for outputting a digital value of a multi value is used, and a feedback is carried out through a one-bit D/A converter for outputting an binary analog value.
In order to achieve the above mentioned object, a first multi-bit xcex94xcexa3 A/D converter in accordance with the present invention comprises an analog adding means for outputting a difference between an analog input signal and an analog feedback signal, an analog integrating means for integrating an output signal of the analog adding means, an analog multiplying means for multiplying an output of the analog integrating means by a predetermined coefficient, a multi-bit quantizing means for quantizing an output of the analog multiplying means with a plurality of bits, and a D/A converting means for converting a digital output signal outputted from the multi-bit quantizing means into an analog signal, the D/A converting means outputting the analog signal as the analog feedback signal in a next sampling time, wherein there is provided a digital processing means receiving the digital output signal outputted from the multi-bit quantizing means, for outputting a sum of the digital output signal and a value obtained by multiplying the digital output signal outputted before a predetermined time, by a predetermined coefficient, and a value obtained by subtracting from an output of the digital processing means a value obtained by differentiating a predetermined quantization noise, is outputted.
The output Y(z) of the above mentioned multi-bit xcex94xcexa3 A/D converter is
Y(z)=aX(z)+(1xe2x88x92zxe2x88x921)Qa(z)
where X(z) is an analog input signal to the multi-bit xcex94xcexa3 A/D converter;
a is a coefficient to be multiplied by the analog multiplying means;
Qa(z) is a quantization noise mixed into with the multi-bit quantizing means.
The digital processing means includes a delay means for holding an output of the multi-bit quantizing means until a next sampling time, a digital multiplying means for multiplying an output of the delay means by a coefficient (axe2x88x921) and a first digital adding means for outputting a sum of the output of the multi-bit quantizing means and an output of the digital multiplying means.
A second multi-bit xcex94xcexa3 A/D converter in accordance with the present invention comprises xe2x80x9ckxe2x80x9d constitution stages (where xe2x80x9ckxe2x80x9d is a positive integer) connected in cascade, each of the constitution stages including an analog adding means receiving an analog input signal and an analog feedback signal for outputting a difference between the analog input signal and the analog feedback signal, an analog integrating means for integrating an output signal of the analog adding means, and an analog multiplying means for multiplying an output of the analog integrating means by a predetermined coefficient, a multi-bit quantizing means for quantizing an output of the analog multiplying means of the xe2x80x9ckxe2x80x9dth stage with a plurality of bits, and a D/A converting means for converting a digital output signal outputted from the multi-bit quantizing means into an analog signal, the D/A converting means outputting the analog signal to the analog adding means of the xe2x80x9ckxe2x80x9d stages, as the analog feedback signal in a next sampling time, wherein there is provided a digital processing means receiving the digital output signal outputted from the multi-bit quantizing means, for outputting a sum of the digital output signal and a value obtained by multiplying the digital output signal outputted before a predetermined time, by a predetermined coefficient, the digital processing means successively performing a similar adding processing for a result of the summing (kxe2x88x921) times, and a value obtained by subtracting from an output of the digital processing means a value obtained by differentiating a predetermined quantization noise, is outputted.
The output Y(z) of the above mentioned multi-bit xcex94xcexa3 A/D converter is
Y(z)=(a1a2 . . . ak)X(z)+(1xe2x88x92zxe2x88x921)kQa(z)
where X(z) is an analog input signal to the multi-bit xcex94xcexa3 A/D converter;
a1, a2, ak are respective coefficients to be multiplied by the analog multiplying means of the first to (k)th stages;
Qa(z) is a quantization noise mixed into with the multi-bit quantizing means.
When k=2, the digital processing means of the second multi-bit xcex94xcexa3 A/D converter includes a first delay means for holding an output of the multi-bit quantizing means until a next sampling time, a first digital multiplying means for multiplying an output of the first delay means by a coefficient (a1a2+a2xe2x88x922), a first digital adding means for outputting a sum of the output of the multi-bit quantizing means and an output of the first digital multiplying means, a second delay means for holding an output of the first delay means until a further next sampling time, a second digital multiplying means for multiplying an output of the second delay means by a coefficient (1xe2x88x92a2), and a second digital adding means for outputting a sum of the output of the first digital adding means and an output of the second digital multiplying means,
When k=3, and the digital processing means of the second multi-bit xcex94xcexa3 A/D converter includes a first delay means for holding an output of the multi-bit quantizing means until a next sampling time, a first digital multiplying means for multiplying an output of the first delay means by a coefficient (a1a2a3+a2a3+a3xe2x88x923), a first digital adding means for outputting a sum of the output of the multi-bit quantizing means and an output of the first digital multiplying means, a second delay means for holding an output of the first delay means until a next sampling time, a second digital multiplying means for multiplying an output of the second delay means by a coefficient (3xe2x88x92a2a3xe2x88x922a3), a second digital adding means for outputting a sum of the output of the digital adding means and an output of the second digital multiplying means, a third delay means for holding an output of the second delay means until a next sampling time, a third digital multiplying means for multiplying an output of the third delay means by a coefficient (a3xe2x88x921), and a third digital adding means for outputting a sum of the output of the second digital adding means and an output of the third digital multiplying means.
A third multi-bit xcex94xcexa3 A/D converter in accordance with the present invention comprises an analog adding means for outputting a difference between an analog input signal and an analog feedback signal, an analog integrating means for integrating an output signal of the analog adding means, an analog multiplying means for multiplying an output of the analog integrating means by a predetermined coefficient, a multi-bit quantizing means for quantizing an output of the analog multiplying means with a plurality of bits, and a D/A converting means for converting a digital output signal outputted from the multi-bit quantizing means into an analog signal, the D/A converting means outputting the analog signal as the analog feedback signal in a next sampling time,
wherein the multi-bit quantizing means includes a n-bit quantizer (where xe2x80x9cnxe2x80x9d is an integer not less than 2) and a most significant bit extractor located at a stage following the n-bit quantizer.
wherein there is provided a digital processing means including a first delay means receiving an output of the n-bit quantizer, for holding the output of the n-bit quantizer for a predetermined time, a first digital multiplying means for multiplying an output of the first delay means by a predetermined coefficient, a first digital adding means for outputting a sum of the output of the n-bit quantizer and an output of the first digital multiplying means, a second delay means receiving a quantization noise mixed into with the most significant bit extractor, for holding the quantization noise for a predetermined time, a second digital multiplying means for multiplying an output of the second delay means by a predetermined coefficient, and a second digital adding means for outputting a sum of the output of the first digital adding means and an output of the second digital multiplying means, as an output of the multi-bit xcex94xcexa3 A/D converter.
The output Y(z) of the third multi-bit xcex94xcexa3 A/D converter is
Y(z)=aX(z)+(1xe2x88x92zxe2x88x921)Qa(z)
where X(z) is an analog input signal to the multi-bit xcex94xcexa3 A/D converter;
a is a coefficient to be multiplied by the analog multiplying means;
(axe2x88x921) is a coefficient to be multiplied by the first digital multiplying means;
a is a coefficient to be multiplied by the second digital multiplying means;
Qa(z) is a quantization noise mixed into with the n-bit quantizer.
A fourth multi-bit xcex94xcexa3 A/D converter in accordance with the present invention comprises two constitution stages connected in cascade, each of the constitution stages including an analog adding means for outputting a difference between an analog input signal and an analog feedback signal, an analog integrating means for integrating an output signal of the analog adding means, and an analog multiplying means for multiplying an output of the analog integrating means by a predetermined coefficient, a multi-bit quantizing means for quantizing an output of the analog multiplying means of the second stage with a plurality of bits, and a D/A converting means for converting a digital output signal outputted from the multi-bit quantizing means into an analog signal, the D/A converting means outputting the analog signal to the analog adding means of each stages, as the analog feedback signal in a next sampling time,
wherein the multi-bit quantizing means includes a n-bit quantizer (where xe2x80x9cnxe2x80x9d is an integer not less than 2) and a most significant bit extractor located at a stage following the n-bit quantizer.
wherein there is provided a digital processing means including a first delay means receiving an output of the n-bit quantizer, for holding the output of the n-bit quantizer for a predetermined time, a first digital multiplying means for multiplying an output of the first delay means by a predetermined coefficient, a first digital adding means for outputting a sum of the output of the n-bit quantizer and an output of the first digital multiplying means, a second delay means for holding the output of the first delay means for a predetermined time, a second digital multiplying means for multiplying an output of the second delay means by a predetermined coefficient, a second digital adding means for outputting a sum of the output of the first digital adding means and an output of the second digital multiplying means, a third digital multiplying means receiving a quantization noise mixed into with the most significant bit extractor, for multiplying the quantization noise by a predetermined coefficient, a third delay means for holding an output of the third digital multiplying means for a predetermined time, a third digital adding means for outputting a sum of the output of the second digital adding means and an output of the third delay means, a fourth digital multiplying means for multiplying an output of the third delay means by a predetermined coefficient, a fourth digital adding means for outputting a sum of the third digital adding means and an output of the fourth digital multiplying means, a fourth delay means for holding an output of the third delay means for a predetermined time, and a fifth digital adding means for outputting a sum of the output of the fourth digital adding means and an output of the fourth delay means, as an output of the multi-bit xcex94xcexa3 A/D converter.
The output Y(z) of the fourth multi-bit xcex94xcexa3 A/D converter is
Y(z)=a1a2X(z)+(1xe2x88x92zxe2x88x921)2Qa(z)
where X(z) is an analog input signal to the multi-bit xcex94xcexa3 A/D converter;
a1 and a2 are respective coefficients to be multiplied by the first and second analog multiplying means;
(a1a2+a2xe2x88x922), (1xe2x88x92a1), a2, and a1 are respective coefficients to be multiplied by the first to fourth digital multiplying means;
Qa(z) is a quantization noise mixed into with the n-bit quantizer.
A fifth multi-bit xcex94xcexa3 A/D converter in accordance with the present invention comprises three constitution stages connected in cascade, each of the constitution stages including an analog adding means for outputting a difference between an analog input signal and an analog feedback signal, an analog integrating means for integrating an output signal of the analog adding means, and an analog multiplying means for multiplying an output of the analog integrating means by a predetermined coefficient, a multi-bit quantizing means for quantizing an output of the analog multiplying means of the final stage with a plurality of bits, and a D/A converting means for converting a digital output signal outputted from the multi-bit quantizing means into an analog signal, the D/A converting means outputting the analog signal to the analog adding means of each stages, as the analog feedback signal in a next sampling time,
wherein the multi-bit quantizing means includes a n-bit quantizer (where xe2x80x9cnxe2x80x9d is an integer not less than 2) and a most significant bit extractor located at a stage following the n-bit quantizer.
wherein there is provided a digital processing means including a first delay means receiving an output of the n-bit quantizer, for holding the output of the n-bit quantizer for a predetermined time, a first digital multiplying means for multiplying an output of the first delay means by a predetermined coefficient, a first digital adding means for outputting a sum of the output of the n-bit quantizer and an output of the first digital multiplying means, a second delay means for holding the output of the first delay means for a predetermined time, a second digital multiplying means for multiplying an output of the second delay means by a predetermined coefficient, a second digital adding means for outputting a sum of the output of the first digital adding means and an output of the second digital multiplying means, a third delay means for holding the output of the second delay means for a predetermined time, a third digital multiplying means for multiplying an output of the third delay means by a predetermined coefficient, a third digital adding means for outputting a sum of the output of the second digital adding means and an output of the third digital multiplying means, a fourth digital multiplying means receiving a quantization noise mixed into with the most significant bit extractor, for multiplying the quantization noise by a predetermined coefficient, a fourth delay means for holding an output of the fourth digital multiplying means for a predetermined time, a fifth digital adding means for multiplying an output of the fourth delay means by a predetermined coefficient, a fourth digital adding means for outputting a sum of the output of the third digital adding means and an output of the fifth digital adding means, a fifth delay means for holding an output of the fourth delay means for a predetermined time, a sixth digital multiplying means for multiplying an output of the fifth delay means by a predetermined coefficient, a fifth digital adding means for outputting a sum of the fourth digital adding means and an output of the fifth digital multiplying means, a sixth delay means for holding an output of the fifth delay means for a predetermined time, and a sixth digital adding means for outputting a sum of the output of the fifth digital adding means and an output of the sixth delay means, as an output of the multi-bit xcex94xcexa3 A/D converter.
The output Y(z) of the fifth multi-bit xcex94xcexa3 A/D converter is
Y(z)=a1a2a3X(z)+(1xe2x88x92zxe2x88x921)3Qa(z)
where X(z) is an analog input signal to the multi-bit xcex94xcexa3 A/D converter;
a1, a2 and a3 are respective coefficients to be multiplied by the first to third analog multiplying means;
(a1a2a3+a2a3+a3xe2x88x923), (3xe2x88x92a2a3xe2x88x922a3), (a3xe2x88x921), a3, (a1a2+a2+1), (a2+2) are respective coefficients to be multiplied by the first to sixth digital multiplying means;
Qa(z) is a quantization noise mixed into with the n-bit quantizer.
With the multi-bit xcex94xcexa3 A/D converters having the above mentioned structure, a quantization noise in a signal band is minimized, and a high precision of conversion can be obtained with a low oversampling ratio.